In general, in a semiconductor device, to improve reliability a burn-in test is performed to remove memory cells with an initial fail probability. The burn-in test involves a test in which a factor exerting a substantial influence on determining failure of a semiconductor device, for example, a voltage is applied to memory cells by raising the voltage to a higher than normal state to induce a stress in the semiconductor device, so as to determine whether or not a fail has occurred in the semiconductor device.
FIG. 1 is a block diagram showing the configuration of a conventional semiconductor device for performing a burn-in test.
Referring to FIG. 1, the conventional semiconductor device includes a data input/output circuit 11 and a test circuit 12. The data input/output circuit 11 is configured to apply an internal command ICMD and first to fourth internal addresses IA<1:4> to the test circuit 12 and receive first to fourth test mode signals TM<1:4>. The data input/output circuit 11 is reset or performs a burn-in test in response to the first to fourth test mode signals TM<1:4>. The test circuit 12 is configured to decode the first to fourth internal addresses IA<1:4> in a state in which the preset internal command ICMD is inputted and generate the first to fourth test mode signals TM<1:4>.
Burn-in test operations performed in the semiconductor device configured in this way will be described with reference to FIG. 2.
First, the test circuit 12 decodes the first to fourth internal addresses IA<1:4> in the state in which the preset internal command ICMD is inputted and generates the first to fourth test mode signals TM<1:4> which are selectively enabled. In detail, the test circuit 12 enables the first test mode signal TM<1> to a logic high level when all the first to fourth internal addresses IA<1:4> have logic low levels, and the test circuit 12 enables the second test mode signal TM<2> to a logic high level when only the fourth internal address IA<4> has a logic high level. Also, the test circuit 12 enables the third test mode signal TM<3> to a logic high level when the second internal address IA<2> and the fourth internal address IA<4> have logic high levels, and the test circuit 12 enables the fourth test mode signal TM<4> to a logic high level when the third and fourth internal addresses IA<3:4> have logic high levels.
Next, the data input/output circuit 11 is reset or performs a burn-in test in response to the first to fourth test mode signals TM<1:4>. That is to say, the data input/output circuit 11 is reset when the first test mode signal TM<1> is enabled, and performs the burn-in test when one of the second to fourth test mode signals TM<2:4> is enabled. In detail, a stress voltage is applied to the memory cells which are connected to odd-numbered word lines of the data input/output circuit 11 when the second test mode signal TM<2> is enabled, a stress voltage is applied to the memory cells which are connected to even-numbered word lines when the third test mode signal TM<3> is enabled, and a stress voltage is applied to the memory cells which are connected to all word lines when the fourth test mode signal TM<4> is enabled.
In the semiconductor device configured as described above, the burn-in test is performed in such a manner that, after controlling word lines to be enabled, by selectively enabling the first to fourth test mode signals TM<1:4> according to level combinations of the first to fourth internal addresses IA<1:4>, a stress voltage is applied to memory cells connected to enabled word lines.
While such a burn-in test is mainly performed in a wafer state, since it is not accompanied by a read operation, whether a fail has occurred in the memory cells applied with the stress voltage is not checked during the burn-in test operations. Therefore, in the conventional semiconductor device, a burn-in test is accompanied by a read operation that is additionally performed in a package state to determine if a fail has occurred in the memory cells.